Last checked: November 11, 2026, 1:14 AM Eastern.

Done

• 3.5, a guest address space, booted on aarch64 and x86_64: check-in 86dd5dbc21
• Glint builds and boots x86_64 with BQ2's toolchain on x86-1: check-in 3cefc212aa
• Boot recordings you can watch in a browser, seven so far, one per milestone, each with what to watch for: the boots page (check-in 8a9569fc4d)
• 3.6, reading a guest image, merged for x86_64: the parser refuses every malformed header with a status; the aarch64 image checks are pending until the seed (check-in 018a86e9f1)
• 3.6b, placing a guest image at boot, merged for x86_64: the boot's CRC matches the host's. Phase 3 is complete on x86_64; its demo passes there, and the aarch64 half is pending until the seed (check-in bf4379a132)
• 4.1 (x86_64), full exception vectors, merged: one dispatcher, and a handled trap resumes the interrupted code (check-in 4233216ded)
• 4.2 (x86_64), a bare-metal test guest, merged: it builds and 3.6b places it; its README fixes the guest call convention (check-in f02087e92d)
• 4.3b, the x86_64 run loop, merged: Mode: hypervisor, and Glint enters the test guest with SVM and decodes its first call (check-in 0c563214cd)
• 4.4 (x86_64), the guest's calls, merged: Phase 4's demo passes on x86_64. The test guest prints through Glint, asks PSCI for its version and powers off (check-in dba10e6aa4); recording
• 4.5, checking guest arguments, merged: one written check for every guest address and length; guest console bytes are filtered (check-in c018ad7b95)
• 4.6 (x86_64), backtraces for Glint's own faults, merged: Phase 4 is complete on x86_64 (check-in 0c038e956f)
• 5.1 (x86_64), decoding guest memory faults, merged for address and access kind (check-in a2cd7a25a9); recording
• 5.2 and 5.3 (x86_64), merged: one device dispatcher, and a 16550 UART on I/O ports that the test guest now prints through (check-in 90f09b3221); recording
• 5.7 (x86_64), lazy guest memory, merged: the test guest backs 32 KiB of its 16 MiB (check-in d42b6f9487)
• aarch64 builds again, inside BQ2's published seed with no client switch. 3.6, 3.6b and every existing aarch64 spec pass there after two spec fixes (check-in 940e9790c7); first aarch64 recording
• 4.1 and 4.6 (aarch64), merged: brk resumes through the EL2 vectors, and faults end with a backtrace (check-in b5930375c8); recording
• 4.2 (aarch64), the test guest builds for aarch64, merged (check-in 5649e3b699)
• 4.3a (i), one vCPU interface for both machines, merged; no behaviour change (check-in afbc684fb4)
• README opens with Glint's purpose and its success checklist; milestone 6 (one language) is done (check-in 1a2a966b51)
• 4.3a (ii) and 4.4 (aarch64), merged: Phase 4's demo passes on both architectures (check-in cbe0a1c3c3); recording
• README: Beagle board names written as proper nouns (check-in b1418659b1), and each term defined where it first appears instead of in a glossary (check-in 40a5be54cb)
• S.8a, a fixed arena for S.8's program tree: 256 nodes in 3,076 bytes, merged (check-in d4e9600a59)
• S.8b, QEMU's Cortex-M0 machine (microbit) in Glint's aarch64 QEMU: a hand-written Thumb image runs and exits with the expected status, merged (check-in afb4181acf)
• S.8c, emit for nine node kinds: ten programs run on QEMU's Cortex-M0 with the expected results, including two that stop on overflow as Crystal does. The instruction encodings aren't yet checked by a disassembler (unverified), because x86-1's LLVM has no ARM target. Merged (check-in 496ed9c188)
• PLAN records your Phase 5 answer: x86 devices through I/O ports only, no instruction decoder on either machine (check-in dd05f46cdb)
• 5.1–5.3 and 5.7 (aarch64), merged: guest loads and stores to a device reach Glint with their size and register, and the aarch64 test guest prints through an emulated PL011 UART (check-in 912a6c0463); recording
• 5.5 and 5.6 (x86_64), merged: the guest finds the same virtio console on PCI, through I/O ports only. Phase 5 is complete on both architectures (check-in d41e247c31); recording
• Boot disks for trying Glint in UTM, aarch64 and x86_64, native and hypervisor (branch utm-images)
• Phase 6 refined: slice order, GICv3 on Arm (what the Beagle SoCs carry), and USB's U.2–U.5 placed after Linux boots (check-in 36f6a2f548)
• U.1, merged: the aarch64 guest finds an emulated xHCI USB controller, reads what it offers, and stops and resets it (check-in d1ece77c05); recording
• 6.1a, merged: Glint's first interrupts on aarch64, through the GICv3; a software interrupt it sends itself is handled and Glint carries on (check-in bf54a5e614); recording
• 6.1b, merged: Glint's first interrupts on x86_64, through the local APIC; both architectures now take interrupts (check-in 8bcd78097c); recording
• 6.2, merged: a 100 Hz timer tick on both architectures, and a sleep command whose ticks match an independent counter (check-in 884ee87288); recording
• 6.3, merged: Zephyr's UART drivers, unmodified, run interrupt-driven on both architectures; the shell idles between keys, and a key typed while a guest runs no longer stops it (check-in 4e310cdb5c); recording
• 6.4a, merged: an Arm guest gets its own emulated interrupt controller; the virtio console and the guest's own timer interrupt it (check-in ad8bd3d14f); recording
• 6.5a (i), merged: Glint writes a devicetree describing exactly the machine it gives an Arm guest, and passes it as Linux expects (check-in b50aa7262e); recording
• 6.5a (ii) part 1, merged: a small UEFI firmware runs as Glint's Arm guest, with a system table, a console, and the devicetree in its configuration table (check-in b9f1011561); recording
• 6.5a (ii) part 2, merged: the guest's firmware loads and starts an EFI application, which finds the devicetree and its command line; along the way a PE header fix for sections with no stored bytes (check-in 935da91f88, check-in 14ce9dcac0); recording
• x86 guests' interrupts decided under your choice A, with the stakes in plain words in PLAN (check-in 124c7a5804)

In progress

• 6.5a (ii) part 3, the guest firmware's memory map, allocation, ExitBootServices and runtime services: the draft works and is being committed as two check-ins (split task)
• 2.4c, native mode on ACPI-only aarch64 firmware (your UTM finding: native says "console not found"): console from SPCR, GIC from MADT, timer from GTDT. Next, then fresh UTM disks, then 6.6 and 6.7a (task, post)
• 6.4b, virtual interrupts on x86 (x2APIC through MSRs, the 8259 and PIT on I/O ports): Codex is building it in a second checkout (task)
• S.8: parked after S.8a–c, since you want the book first (check-in 5e0694da5a)
• PLAN.md's BeagleConnect roadmap: waiting for the board list, which I can't read in the console posts (post 0f2fb5db9d)
• Track U, USB: guests get an emulated xHCI controller (aarch64 only; x86 guests can't reach it under A). U.1, its register file, comes after Phase 5; U.2–U.5 after Phase 6 and before Phase 7 (plan, check-in dd05f46cdb)

Waiting on the maintainer

• Nothing right now. You left the interrupt design to Glint; only a choice that crosses your I/O-port decision or adds an instruction decoder comes back to you