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| Comment: | PLAN: x86 guests' interrupts decided under choice A
Claim: What Linux sees now gives x86 guests the local APIC as x2APIC through MSRs, the 8259 and PIT on I/O ports, plain MSI later, and the TSC; no IOAPIC or HPET. The stakes note says decided, with the timer calibrated against the PIT and CPUID added only if 6.7b shows Linux needs it. The decision log records it. The Arm row says GICv3, as 6.1a decided. Passage: the maintainer, relayed in glint 5c447d1377: 'If Glint understands and finds the trade-offs reasonable, it may architect how it handles interrupts and access exceptions.' Demonstration: the design crosses neither the I/O-port decision nor adds a decoder: x2APIC accesses arrive as MSR exits with number and value, and the 8259 and PIT are port devices on 5.2's dispatcher. Size: about 20 lines in PLAN.md. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX |
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| Timelines: | family | ancestors | descendants | both | trunk |
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124c7a580458acd343b7559b8be1c781 |
| User & Date: | x86-1-glint 2026-11-11 06:13:35.724 |
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2026-11-11
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| 06:14 |
docs/tasks/6.4b.md: virtual interrupts on x86, as PLAN now decides
Claim: the task for 6.4b in two check-ins: (i) the guest's local APIC as x2APIC through intercepted MSRs, CPUID reporting x2APIC, VMCB injection behind one call (V_IRQ or EVENTINJ), the guest's APIC timer, and hlt as a wait; (ii) the 8259 pair and ELCR, the PIT with channel 2 through port 0x61, and the virtio console's INTx through the 8259. No IOAPIC, no HPET, no decoder. Passage: PLAN, What Linux sees, x86 guests' interrupts under choice A (decided Nov 11, 2026). Demonstration: the VMCB fields named are QEMU 11.1.2 target/i386/svm.h lines 9-10, 24-25 and 42-53. Size: one task file. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX Leaf check-in: 463e61cba4 user: x86-1-glint tags: trunk | |
| 06:13 |
PLAN: x86 guests' interrupts decided under choice A
Claim: What Linux sees now gives x86 guests the local APIC as x2APIC through MSRs, the 8259 and PIT on I/O ports, plain MSI later, and the TSC; no IOAPIC or HPET. The stakes note says decided, with the timer calibrated against the PIT and CPUID added only if 6.7b shows Linux needs it. The decision log records it. The Arm row says GICv3, as 6.1a decided. Passage: the maintainer, relayed in glint 5c447d1377: 'If Glint understands and finds the trade-offs reasonable, it may architect how it handles interrupts and access exceptions.' Demonstration: the design crosses neither the I/O-port decision nor adds a decoder: x2APIC accesses arrive as MSR exits with number and value, and the 8259 and PIT are port devices on 5.2's dispatcher. Size: about 20 lines in PLAN.md. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 124c7a5804 user: x86-1-glint tags: trunk | |
| 06:11 |
PLAN: the stakes of x86 guests' interrupt controllers under choice A
Claim: next to What Linux sees, PLAN records the open question about x86 guests' interrupts in plain words: the proposal (x2APIC through MSRs, the 8259 and PIT on ports, no IOAPIC or HPET), and what it costs or keeps for real PCs, one-CPU guests, several-CPU guests (MSI fits A; MSI-X doesn't), Linux's timer calibration, and changing course later. Unchecked points are marked. Passage: The One Place's relay of the maintainer's question, glint ca4e0e5caa: record the stakes in plain words next to the change, whatever the maintainer decides. Demonstration: each register claim is cited to QEMU 11.1.2 (hw/intc/ioapic.c, hw/intc/i8259.c, hw/timer/hpet.c, hw/virtio/virtio-pci.c); the chipset and Linux claims are marked unchecked. Size: 40 lines added to PLAN.md. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 8e7ac49ca9 user: x86-1-glint tags: trunk | |