Branch: slice/2.4c. Commit only there; never to trunk. One check-in. Past ~400 non-spec lines, stop, commit nothing, and say so (rule 3).

Why now. The maintainer booted the aarch64 UTM disk on a Mac. Hosted mode works; native answers console not found. UTM gives no way to turn ACPI off, so its edk2 firmware hands Glint ACPI tables and no devicetree, and native mode finds its console only through the devicetree's stdout-path (boot/mode.cr line 92), as 2.4a made it (glint forum 396ebb66f3). This is a Phase 2 addendum, like 2.7c, slotted in before 6.6 because the maintainer is using the disk now.

Building: aarch64 inside BQ2's seed, exactly as docs/tasks/4.1a.md shows; x86_64 outside it, only to show it's unchanged.

Read first:

• docs/phases/02-organization.md: slices 2.4a and 2.4b (the devicetree on aarch64, ACPI on x86_64), and PLAN's principle on standard interfaces (No BSPs, principle 6): SPCR, MADT and GTDT are published ACPI tables, as the devicetree is.
• boot/acpi.cr (2.4b's checked table lookup, used on x86_64, and 6.1b's MADT reading), boot/fdt.cr, boot/mode.cr, boot/efi_main.cr, and how 6.1a (boot/gic.cr) and 6.2 (boot/timer.cr) find the GIC and the timer from the devicetree today.
• How the console's address reaches Zephyr's PL011 driver: Track Z's generated devicetree and the check that the firmware's description matches the class Glint was built for (PLAN decision log, upstream devicetrees as data).
• QEMU 11.1.2 hw/arm/virt-acpi-build.c: spcr_setup (line 765, the interface type and base address it writes), build_madt (GICD, GICR and GICC entries), build_gtdt (timer interrupts); and hw/acpi/aml-build.c build_spcr. These stand in for the ACPI and SPCR specifications, which aren't in the workspace. Cite each field you read.
• U-Boot 2026.07 configs/qemu_arm64_acpi_defconfig and src/glint/uboot/config.cr (how the project builds U-Boot).

Claim. On aarch64 firmware that gives ACPI and no devicetree, native mode finds its console UART from SPCR, its GIC from MADT and its timer interrupt from GTDT, and runs as it does with a devicetree. With a devicetree present nothing changes: the devicetree stays the first source.

Passage. The plan's principle 6 (standard interfaces need no board support package). Quote it from PLAN.md.

Make:

• A test machine with ACPI and no devicetree. Build a second aarch64 U-Boot from qemu_arm64_acpi_defconfig (into its own build directory, build/uboot/aarch64-acpi), so it passes QEMU's ACPI tables. If it still passes a devicetree as well, find how to boot with ACPI only (a U-Boot setting or environment variable, not a Glint flag that pretends), and say what you used and why. bin/glint-run aarch64 --firmware acpi selects it.
• boot/acpi.cr on aarch64: SPCR (interface type: PL011 or SBSA generic UART, both accepted; base address), MADT's GICD and GICR entries (and GICC's redistributor field when there's no GICR entry), GTDT's EL2 and EL1 physical timer interrupts. All through 2.4b's checked lookup; bad lengths and checksums refused, as now.
• Native mode's console: when there's no devicetree, the console comes from SPCR. The address must match the PL011 Glint's Zephyr build expects, as the devicetree path requires today; a mismatch is refused with a line naming both addresses, not guessed around.
• 6.1a and 6.2 on ACPI: the GIC and the timer interrupt come from MADT and GTDT when there's no devicetree. If MADT names a GICv2, print GIC: v2, not supported and continue without interrupts, as GIC: none does.
• The boot's hardware line says which source it used, e.g. Hardware: ACPI (SPCR, MADT, GTDT) or Hardware: devicetree.

Specs.

• Host: SPCR, MADT and GTDT parsing over tables recorded from QEMU's virt (record them reproducibly, as 6.1b recorded its MADT), and over malformed ones.
• Boots, in the seed: bin/glint-run aarch64 --firmware acpi --type native --type 'cat "hello.txt"' --type interrupt --type 'sleep 1' shows the ACPI hardware line, native mode entered, the file, Interrupt: SGI 1 handled and the sleep line. Every existing aarch64 boot passes unedited on the devicetree firmware.

Constraints. BQ2 tools only; aarch64 via the seed. No start-up initialisers and no heap; the image check passes on both images. No change to x86_64: its boots pass unedited. No new function over 2 KiB, and no existing one pushed over it, in the built image. About 250 non-spec lines. Report every constraint you couldn't meet; never change one silently.

Demonstration. The host specs; in the seed, the whole aarch64 boot suite and the image and small-target specs; outside it, the whole x86_64 boot suite and crystal spec with ZEPHYR_SRC set; crystal tool format --check.

Check-in comment. Rule 2's four parts.