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Overview
Comment:Merge 4.3a (ii) and 4.4 (aarch64): the EL2 run loop and HVC calls

Reviewed against docs/tasks/4.3a-split.md part (ii); verdict merge. Phase 4's demo passes on both architectures.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX

Downloads: Tarball | ZIP archive
Timelines: family | ancestors | descendants | both | trunk
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SHA3-256: cbe0a1c3c3cf775d6a740044f681c7db801b96ecb700af56de3d8e1b9b2934a9
User & Date: x86-1-glint 2026-11-09 22:39:10.918
Context
2026-11-09
22:40
README: a 'Words used here' section, so a novice can follow without outside help

Claim: the README top gains the maintainer's short glossary at its end: processor architecture, microcontroller, memory and KiB, flash, interrupt, scheduling, compiler, UEFI, Kconfig/flex/bison/parser generators, and xv6. It is used as written.

Passage: The One Place's relay of the maintainer's addition (glint c16cfbd8e5).

Demonstration: the section sits after 'The virtues behind it' and before 'Building', the end of the top the maintainer gave.

Size: 24 lines added.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 44f971de24 user: x86-1-glint tags: trunk

22:39
Merge 4.3a (ii) and 4.4 (aarch64): the EL2 run loop and HVC calls

Reviewed against docs/tasks/4.3a-split.md part (ii); verdict merge. Phase 4's demo passes on both architectures.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: cbe0a1c3c3 user: x86-1-glint tags: trunk

22:39
4.3a (ii) and 4.4 (aarch64): the EL2 run loop and HVC calls

Claim: Glint is a hypervisor on aarch64 too. Hypervisor mode is granted when native is granted and Glint entered at EL2; otherwise Mode: says why. El2::State, behind 4.3a (i)'s vCPU interface, enters the guest at EL1 with eret under stage 2 over 3.5's guest space. HCR_EL2 sets VM, FMO/IMO/AMO, TWI/TWE, TSC, TVM/TRVM and RW, each cited to QEMU 11.1.2 target/arm/cpu.h; VTTBR/VTCR come from the guest space. Glint's callee-saved registers, EL1 state and its own sp are saved first. Glint's sp is saved with mov, not by writing SP_EL0, and SP_EL0 is touched only after msr SPSel, #1, the first attempt's finding. Exits from the guest (vectors 8-11) copy the guest frame, FAR and HPFAR into the state, restore Glint's EL1 state, return to SPSel 0 and Glint's sp, and return to run's caller. ESR's EC gives the neutral reason: HVC64 is a call, and a lower-EL data abort is a memory fault, with the size and register when ISV is set. HVC calls go through the shared GuestCalls with no RIP advance, since ELR already points past the hvc. 5.7's lazy memory works unchanged.

Passage: Hailperin ยง7.5.2: 'the VMM keeps track of each virtual machine's simulated mode.' The guest's mode comes from the saved SPSR.

Demonstration: Phase 4's demo on aarch64. The reviewer booted, on x86-1 with the image built inside BQ2's seed, bin/glint-run aarch64 --mode hypervisor --guest build/aarch64/guest/test.efi. It printed 'Mode: hypervisor', 'test guest: started', 'test guest: PSCI version 0x0000000000000002', 'test guest: console call works', 'VM: guest powered off' and 'VM: guest memory 20 KiB backed of 16384 KiB', then the prompt. That's 5 pages: the 16 KiB image and one stack page; the guest's MMU is off, so it has no tables. With --no-virtualization: 'Mode: native (hypervisor requested; EL2 not available)'. The fault guest reports 'VM exit: memory fault read 0x41000000'. Codex reports, in the seed, the aarch64 phase 4, vcpu and fault boots at 19 examples, 0 failures, 0 pending, and the EL2 state and image-check specs at 7 examples, 0 failures. Outside the seed, the x86_64 boots give 32 examples, 0 failures, 4 pending (aarch64). Format passes. Codex wrote it from docs/tasks/4.3a-split.md part (ii); the reviewer checked the HCR_EL2 value bit by bit against its comment and made no changes.

Size: +237/-18 non-spec lines; largest new function El2::State#initialize, 892 bytes; BOOTAA64.EFI 201,728 bytes, BOOTX64.EFI 213,504 bytes.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX Leaf check-in: f6b54ae268 user: x86-1-glint tags: slice/4.3a-ii

22:37
README: Glint's purpose and definition of success, replacing the stale opening and Status

Claim: README.md now opens with the text worked out by the maintainer and The One Place: what Glint is for, what it's made of (BQ2 defined where it first appears), how it's shaped, how it's built, a six-milestone success checklist, and the four virtues. The old opening and its Status section (Phase 1 and Track T done, Phase 2 next) are gone. Building, Layout, Working on Glint and Licence follow unchanged. Milestones 1-5 are marked not yet. Milestone 6 is marked done, with links to the x86_64 and aarch64 builds on x86-1.

Passage: The One Place's request (glint 5e43b80618, text in 0f2fb5db9d), from the maintainer's console thread (ocx-console f561f86cc3, d714496afc, 874aec9e34, 09cd94458a).

Demonstration: for milestone 6, command -v finds no python3, python, flex, bison, kconfig-conf, mconf, meson or ninja on x86-1, nor inside BQ2's seed. Glint's x86_64 build (3cefc212aa) and its aarch64 build inside the seed (940e9790c7) both ran there. The text above the checklist is used as given.

Size: the first 47 lines replaced by 118.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 1a2a966b51 user: x86-1-glint tags: trunk

Changes
Unified Diff Side-by-Side Diff Patch
Changes to boot/efi_main.cr.
Changes to boot/el2.cr.
Added boot/el2_aarch64.S.
Changes to boot/privilege.cr.
Changes to boot/vcpu.cr.
Changes to boot/vectors_aarch64.S.
Changes to spec/el2_state_spec.cr.
Changes to spec/run/fault_spec.cr.
Changes to spec/run/phase4_spec.cr.
Changes to spec/run/vcpu_spec.cr.
Added spec/support/arm_vcpu_boot.cr.
Changes to tools/glint_build.cr.