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| Comment: | Merge 6.1b: the x86 local APIC and IOAPIC
Reviewed against docs/tasks/6.1b.md; verdict merge. Glint finds both controllers in the recorded-and-reproducible q35 MADT, masks the 8259s, enables the xAPIC with every LVT entry masked, masks all 24 IOAPIC entries (N from the IOAPIC's version register), and takes vectors 0x20-0xff through 4.1's dispatcher on IST1, which keeps the compiler's red zone safe. 338 changed non-spec lines: over the ~250 target, under the 400 stop. The reviewer booted interrupt twice then cat outside the seed: the APIC line, two 'Interrupt: vector 0x41 handled' / 'interrupt: resumed' pairs, the file; exit 0. aarch64 unchanged in the seed (29 boot examples, per Codex). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX |
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| User & Date: | x86-1-glint 2026-11-11 01:47:47.727 |
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2026-11-11
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| 01:48 |
docs/boots: Glint's first interrupts on x86_64, recorded
Claim: the boots page gains 6.1b: Glint brings up the local APIC and IOAPIC and handles two interrupts it sends itself. Passage: the maintainer's request for a recording at each milestone (ocx-console 40c80385db). Demonstration: the cast is the file bin/glint-run wrote on x86-1 at the merge 8bcd78097c's tree; it exited 0 with the lines the entry quotes. Size: one cast, one page entry. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 531c5f6a2f user: x86-1-glint tags: trunk | |
| 01:47 |
Merge 6.1b: the x86 local APIC and IOAPIC
Reviewed against docs/tasks/6.1b.md; verdict merge. Glint finds both controllers in the recorded-and-reproducible q35 MADT, masks the 8259s, enables the xAPIC with every LVT entry masked, masks all 24 IOAPIC entries (N from the IOAPIC's version register), and takes vectors 0x20-0xff through 4.1's dispatcher on IST1, which keeps the compiler's red zone safe. 338 changed non-spec lines: over the ~250 target, under the 400 stop. The reviewer booted interrupt twice then cat outside the seed: the APIC line, two 'Interrupt: vector 0x41 handled' / 'interrupt: resumed' pairs, the file; exit 0. aarch64 unchanged in the seed (29 boot examples, per Codex). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 8bcd78097c user: x86-1-glint tags: trunk | |
| 01:46 |
6.1b: xAPIC and IOAPIC discovery, masking and resumable self-IPIs
Claim: Native x86_64 finds the enabled CPU and first IOAPIC in the checked ACPI MADT, checks IA32_APIC_BASE, maps the controller pages as devices, masks both PICs, all LVTs and IOAPIC entries, and software-enables xAPIC. Vectors 32-255 use the existing dispatcher and iretq; handlers precede EOI, spurious vector 255 gets none, and unhandled vectors are reported once. The interrupt command alone enables IF, handles vector 0x41, disables IF, and resumes. IRQs use IST1 to preserve the compiler's red zone. Arm's path and all existing boot tests are unchanged (only interrupt_spec's x86 block changes). Passage: MOS4/5 section 5.1.5, Interrupts Revisited. The full text is not available in this checkout; paraphrase: save interrupted execution, dispatch the interrupt handler, acknowledge completion and restore execution so the interrupted work continues. QEMU 11.1.2 is the register-layout authority, cited beside the code; its EPYC FEAT_1_ECX lacks x2APIC. Demonstration: Outside the seed: crystal spec spec/apic_spec.cr spec/acpi_spec.cr spec/gic_spec.cr 19 examples, no failures/errors/pending. ZEPHYR_SRC=/workspace/src/zephyr-src LD_LIBRARY_PATH=/usr/lib64 crystal spec 1381 examples, 0 failures, 0 errors, 57 pending ZEPHYR_SRC=/workspace/src/zephyr-src QEMU_SRC=/workspace/src/qemu-11.1.2 UBOOT_SRC=/workspace/src/u-boot-2026.07 crystal spec spec/run --example x86_64 28 examples, no failures/errors/pending. The interrupt example sends twice, sees both handled/resumed pairs and reads hello.txt. crystal run tools/record_madt.cr Repeats the recorded 120-byte q35 MADT byte-for-byte; SHA256 730d87a32397365641ca2c58beb3832119c66813e98774fb482571f08668143c. Boot reports local 0xfee00000 id 0, IOAPIC 0xfec00000, 24 lines. N = version register maximum redirection index 23 + 1, matching QEMU include/hw/intc/ioapic.h IOAPIC_NUM_PINS=24. crystal tool format --check Passes. Inside the exact 4.1a seed namespace, with cd /workspace/v54: bq2 sysroot-namespace --rootfs=/workspace/seed/rootfs --bind=/workspace:/workspace -- /bin/sh -c 'cd /workspace/v54 && export ZEPHYR_SRC=/workspace/src/zephyr-src QEMU_SRC=/workspace/src/qemu-11.1.2 UBOOT_SRC=/workspace/src/u-boot-2026.07 HOME=/workspace/seed/home GLINT_UBOOT_BUILD_DIR=build/uboot GLINT_QEMU_AARCH64=build/qemu-aarch64/qemu-system-aarch64 LD_LIBRARY_PATH=/usr/lib64 && bin/glint-build aarch64 && crystal spec spec/run --example aarch64' 29 examples, no failures/errors/pending. With the same namespace/export prefix: crystal spec spec/image_initialization_spec.cr spec/small_target_spec.cr spec/apic_spec.cr spec/acpi_spec.cr spec/gic_spec.cr 25 examples, no failures/errors/pending; both linked images have no startup initializers; Cortex-M0+ checks pass. crystal spec spec/efi_image_spec.cr spec/pe_image_spec.cr spec/elf_dialect_spec.cr --example aarch64 478 examples, no failures/errors/pending. crystal spec spec/run/glint_run_spec.cr --example "fails a wrong expected line" crystal spec spec/run/glint_run_spec.cr --example "writes a FAT16 ESP" One example each, both pass. Builder calls for x86 in shared image checks use the current image; x86 compilation was outside the seed. Size: +319/-19 non-spec lines, 338 changed, net +300 (including comments and blanks; excludes specs and fixtures). Above the approximate 250-line aim, below the 400-line stop bound. Largest new image function: Apic.controllers, 1832 bytes by llvm-nm --print-size --size-sort --radix=d. EFI image bytes before -> after: aarch64 238592 -> 238592; x86_64 238080 -> 250368. No other constraint unmet; BQ2 tools only, no Python, no startup initializers or heap use in the new interrupt path. Leaf check-in: 6b60e4b5f3 user: x86-1-glint tags: slice/6.1b | |
| 01:24 |
docs/tasks/6.1b.md: the x86 local APIC and IOAPIC
Claim: the task for 6.1b, 6.1a's twin on x86_64: Glint finds the local APIC and IOAPIC in the ACPI MADT, masks the 8259 PICs, enables the local APIC, and takes a self-IPI on vector 0x41 through 4.1's dispatcher, with the same command and lines as on aarch64. Passage: docs/phases/06-interrupts-drivers.md, slice 6.1b. Demonstration: QEMU 11.1.2's EPYC model lists no x2APIC in FEAT_1_ECX (target/i386/cpu.c), so the task uses the memory-mapped xAPIC; IO_APIC_DEFAULT_ADDRESS is 0xfec00000 (include/hw/intc/ioapic.h:24). Size: one task file. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 8a1d10ca22 user: x86-1-glint tags: trunk | |