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| Comment: | Merge 6.2: timer interrupts on both architectures
Reviewed against docs/tasks/6.2.md; verdict merge. A 100 Hz tick through 6.1's controllers: the generic timer on aarch64 (EL2 physical at EL2, EL1 physical at EL1, CNTFRQ 1 GHz on QEMU), and the local APIC timer on x86_64, calibrated against the ACPI PM timer at about 996 MHz. The tick runs only during sleep, so guests are unaffected until 6.4. 312 changed non-spec lines with documentation: over the ~250 target, under the 400 stop. The reviewer ran sleep then cat: aarch64 in the seed exited 0; x86_64 printed 'Timer: local APIC, 995884398 Hz counter, 100 Hz tick' and 'sleep: 2 s, 200 ticks (counter agrees)', then the file; exit 0. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX |
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| Downloads: | Tarball | ZIP archive |
| Timelines: | family | ancestors | descendants | both | trunk |
| Files: | files | file ages | folders |
| SHA3-256: |
884ee872887e01e96525254e26360ca9 |
| User & Date: | x86-1-glint 2026-11-11 02:03:04.976 |
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2026-11-11
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| 02:03 |
docs/boots: the 100 Hz timer tick and sleep, recorded
Claim: the boots page gains 6.2 on x86_64: Glint calibrates the local APIC timer and sleeps two seconds on its tick. Passage: the maintainer's request for a recording at each milestone (ocx-console 40c80385db). Demonstration: the cast is the file bin/glint-run wrote on x86-1 at the merge 884ee87288's tree; it exited 0 with the lines the entry quotes. Size: one cast, one page entry. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 6ddc6690b1 user: x86-1-glint tags: trunk | |
| 02:03 |
Merge 6.2: timer interrupts on both architectures
Reviewed against docs/tasks/6.2.md; verdict merge. A 100 Hz tick through 6.1's controllers: the generic timer on aarch64 (EL2 physical at EL2, EL1 physical at EL1, CNTFRQ 1 GHz on QEMU), and the local APIC timer on x86_64, calibrated against the ACPI PM timer at about 996 MHz. The tick runs only during sleep, so guests are unaffected until 6.4. 312 changed non-spec lines with documentation: over the ~250 target, under the 400 stop. The reviewer ran sleep then cat: aarch64 in the seed exited 0; x86_64 printed 'Timer: local APIC, 995884398 Hz counter, 100 Hz tick' and 'sleep: 2 s, 200 ticks (counter agrees)', then the file; exit 0. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 884ee87288 user: x86-1-glint tags: trunk | |
| 02:01 |
6.2: command-scoped 100 Hz timers and sleep on aarch64 and x86_64
Claim: Timer.start/stop/ticks drive the generic physical timer at EL2 or EL1 and the local APIC timer through the existing controller tables and trap dispatcher. sleep 1..10 idles between ticks, stops before returning, and checks the elapsed count against CNTPCT or the ACPI PM counter. APIC frequency is calibrated once from firmware's PM port, including wraps. Passage: xv6 6.4, Timer interrupts (text not present locally; paraphrase): periodic timer interrupts let the kernel count time, and the handler schedules the next interrupt. Hailperin 2.5 supplies the later preemption motivation; MOS4/5 5.5 discusses clocks. docs/phases/06-interrupts-drivers.md 6.2 is the specification. docs/timer.md and inline citations name QEMU 11.1.2's timer registers, PPIs, APIC mode/divisor and FADT PM counter. Demonstration: inside BQ2's seed, with the environment in docs/tasks/4.1a.md and cd /workspace/v54: bin/glint-build aarch64; crystal spec spec/run --example aarch64: 31 examples, no failures/errors/pending. Serialized wrong-expected-line and FAT16 harness checks each pass. Timer boots at EL2 and EL1 each print 1000000000 Hz and sleep: 1 s, 100 ticks (counter agrees). crystal spec spec/timer_spec.cr spec/image_initialization_spec.cr spec/efi_image_spec.cr spec/pe_image_spec.cr spec/small_target_spec.cr: 964 examples pass. Outside, with the source paths set, crystal spec spec/run --example x86_64: 29 examples pass; local APIC measures 996044495 Hz and sleep counts 100 ticks with counter agreement. LD_LIBRARY_PATH=/usr/lib64 ZEPHYR_SRC=/workspace/src/zephyr-src crystal spec: 1386 examples, 0 failures, 0 errors, 59 expected unavailable-target/source pending. crystal tool format --check passes. Initial overlapping Arm harness execution shared the ESP and failed a mode assertion; a loaded timer measured 102 counter ticks. The complete serialized rerun passed without changing existing specs. Size: 311 added and 1 removed non-spec lines (312 changed), above the approximate 250-line target and below 400. Specs add 63 lines. EFI image bytes before -> after: aarch64 238592 -> 246784; x86_64 250368 -> 254464. Largest new function: Fdt#compatible_property on Arm, 1988 bytes (<2048). No new heap allocation or startup initializer; image and small checks pass. Leaf check-in: a4f82d95d1 user: x86-1-glint tags: slice/6.2 | |
| 01:48 |
docs/tasks/6.2.md: timer interrupts on both architectures
Claim: the task for 6.2: a 100 Hz tick through 6.1's controllers on both machines, the generic timer on aarch64 (EL2 or EL1 physical) and the local APIC timer on x86_64, calibrated against the ACPI PM timer; a sleep command that counts ticks and checks them against a free-running counter. Passage: docs/phases/06-interrupts-drivers.md, slice 6.2; xv6 6.4. Demonstration: the timer PPIs are QEMU 11.1.2 include/hw/arm/bsa.h:29-33 (EL2 physical 26, EL1 physical 30); the PM timer's place is hw/i386/acpi-build.c:183. Size: one task file. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: e57176dfad user: x86-1-glint tags: trunk | |