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| Comment: | PLAN: x86 devices through I/O ports only; Track U, USB for guests as an emulated xHCI
Claim: the maintainer's answer on Phase 5 is in the plan. On x86_64 guests reach Glint's devices only through I/O ports, with no instruction decoder; 5.5's virtio-pci uses configuration ports 0xcf8/0xcfc and virtio's legacy I/O-port BAR. On aarch64 the data-abort syndrome gives size and register for single-register loads and stores, so no decoder is needed there. A new Track U (docs/phases/U-usb.md) places USB, Glint's primary peripheral: guests see an emulated xHCI; Glint keeps the real controller. U.1 (register file) after Phase 5; U.2-U.5 (rings, a virtual keyboard, Glint's own xHCI driver, forwarding) after Phase 6 and before Phase 7; U.6 on Beagle hardware with Phase 13. The emulated controller is aarch64-only, since xHCI's registers are only memory-mapped. Open question 2 is answered. Passage: the maintainer, relayed in glint 366ac226de: 'For x86, that sounds like it makes sense... Emulating the USB controller is the primary peripheral to be captured by Glint.' xv6 6, on what a driver does. Demonstration: each fact is cited. QEMU 11.1.2 translate-a64.c sets iss_valid only for LDR/STR without writeback; hcd-xhci-pci.c:165 registers xHCI's BAR 0 as 64-bit memory; virtio-pci.c:2155 the legacy I/O BAR. U-Boot 2026.07: AM62x has snps,dwc3 and J722S cdns,usb3, both calling xhci_register in host mode; xhci-generic.c binds generic-xhci. Linux's generic-xhci binding is marked unverified (no Linux source here). Size: PLAN.md about 35 lines, 05-page-faults.md 5 lines, U-usb.md 100 lines. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX |
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| Downloads: | Tarball | ZIP archive |
| Timelines: | family | ancestors | descendants | both | trunk |
| Files: | files | file ages | folders |
| SHA3-256: |
dd05f46cdbe4413027afe1a5335cd3b2 |
| User & Date: | x86-1-glint 2026-11-10 21:38:26.808 |
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2026-11-10
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| 22:25 |
Merge 5.1-5.3 and 5.7 (aarch64): memory-mapped devices and a PL011 UART
Reviewed against docs/tasks/5.3a.md; verdict merge. The task asked both for unclaimed memory reads to return all ones and for the fault guest's read at 0x41000000 to stop; Codex resolved the conflict by dispatching only faults inside a registered memory range, which keeps both. The reviewer agrees and booted the PL011 demo in BQ2's seed: the guest's lines, 'VM: guest powered off', 20 KiB backed, exit 0. The 2 KiB function limit is still exceeded only by the shell matcher's existing functions, unchanged here. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 912a6c0463 user: x86-1-glint tags: trunk | |
| 22:01 |
utm-images: Glint boot disks for UTM, built from trunk dd05f46cdb
Claim: four raw boot disks the maintainer can open in UTM: aarch64 and x86_64, each native and hypervisor (with the test guest), made by src/glint/run/esp.cr from images built at trunk dd05f46cdb. They live on this branch, not trunk, because this login can't write unversioned files. Passage: The One Place's relay, glint 15cb2cfbe8. Demonstration: under the project's QEMU 11.1.2 and U-Boot 2026.07 (not edk2 or UTM), both hypervisor disks boot to 'Mode: hypervisor', the guest's lines, 'VM: guest powered off' and the memory line (20 KiB aarch64, 32 KiB x86_64). sha256: aarch64-native efb6247e..., aarch64-hypervisor c52954b4..., x86_64-native 664820e7..., x86_64-hypervisor 369c325d.... Size: four 33 MiB disks (about 125 KiB each compressed) and a README. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX Leaf check-in: aa797404bb user: x86-1-glint tags: utm-images | |
| 21:38 |
PLAN: x86 devices through I/O ports only; Track U, USB for guests as an emulated xHCI
Claim: the maintainer's answer on Phase 5 is in the plan. On x86_64 guests reach Glint's devices only through I/O ports, with no instruction decoder; 5.5's virtio-pci uses configuration ports 0xcf8/0xcfc and virtio's legacy I/O-port BAR. On aarch64 the data-abort syndrome gives size and register for single-register loads and stores, so no decoder is needed there. A new Track U (docs/phases/U-usb.md) places USB, Glint's primary peripheral: guests see an emulated xHCI; Glint keeps the real controller. U.1 (register file) after Phase 5; U.2-U.5 (rings, a virtual keyboard, Glint's own xHCI driver, forwarding) after Phase 6 and before Phase 7; U.6 on Beagle hardware with Phase 13. The emulated controller is aarch64-only, since xHCI's registers are only memory-mapped. Open question 2 is answered. Passage: the maintainer, relayed in glint 366ac226de: 'For x86, that sounds like it makes sense... Emulating the USB controller is the primary peripheral to be captured by Glint.' xv6 6, on what a driver does. Demonstration: each fact is cited. QEMU 11.1.2 translate-a64.c sets iss_valid only for LDR/STR without writeback; hcd-xhci-pci.c:165 registers xHCI's BAR 0 as 64-bit memory; virtio-pci.c:2155 the legacy I/O BAR. U-Boot 2026.07: AM62x has snps,dwc3 and J722S cdns,usb3, both calling xhci_register in host mode; xhci-generic.c binds generic-xhci. Linux's generic-xhci binding is marked unverified (no Linux source here). Size: PLAN.md about 35 lines, 05-page-faults.md 5 lines, U-usb.md 100 lines. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: dd05f46cdb user: x86-1-glint tags: trunk | |
| 21:32 |
docs/tasks/S.1.md: S.1 builds inside BQ2's seed, facts checked
Claim: S.1 no longer waits on x86-1's LLVM. Inside BQ2's seed (LLVM 18.1.7 with X86, ARM and AArch64), Crystal 1.19.1 cross-compiles --target arm-none-eabi --mcpu cortex-m0plus. The two facts the task marked unchecked are now checked: --mattr +thumb-mode isn't needed, and llvm-readelf -A gives CPU_arch 'ARM v6S-M', ARM_ISA_use 'Not Permitted', THUMB_ISA_use 'Thumb-1'. Board names follow the proper-noun rule. Passage: The One Place's relay (glint c3ae75dfc6): the seed's LLVM has ARM; schedule S.1 after the book work if that is enough. Demonstration: the reviewer built a one-function Crystal file inside the seed with and without +thumb-mode; both disassemble to 'adds r0, r0, r1; bx lr', and readelf printed the values quoted. Size: about 12 lines changed in one task file. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 9fe6789433 user: x86-1-glint tags: trunk | |