Claim: docs/tasks/4.3a-split.md divides 4.3a after the first run stopped at 432 non-spec lines. (i) separates Vcpu from SVM so both machines share one interface, with no behaviour change. (ii) adds the EL2 backend, aarch64 hypervisor mode and 4.4's aarch64 half. It records the first run's finding: writing SP_EL0 with msr from ordinary code is UNDEFINED while Glint runs on SP_EL0, and that caused the attempt's panic.

Passage: docs/WORKFLOW.md, rule 3 (stop past ~400 lines and split).

Demonstration: the attempt's report and boot log (ESR 0x2000000 at the msr SP_EL0) are kept in the session scratchpad for part (ii). 4.2's aarch64 half is merged at 5649e3b699.

Size: one new task.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 653dca15b6 user: x86-1-glint tags: trunk

Claim: guest/test/call_aarch64.S gives the test guest its aarch64 entry (align sp, call test_guest_main) and guest_call (hvc #0, since AAPCS64 already puts the ID and arguments in x0-x3), plus guest_halt (a wfi loop). bin/glint-build test-guest aarch64 and fault-guest aarch64 build it as on x86_64. On aarch64 all its text goes through GLINT_CONSOLE_WRITE, because there's no 16550; 5.3's PL011 will change that. The lines are the same as on x86_64.

Passage: slice 4.2: 'A guest this small isolates Glint's behaviour from a large guest's, so any failure in this phase points at Glint.'

Demonstration: inside BQ2's seed, both guests build (12,800 bytes each). spec/test_guest_build_spec.cr gives 4 examples, 0 failures, 0 pending there: 3.6 parses the image, and llvm-objdump shows hvc #0 after the three IDs. Outside the seed, the x86_64 half still passes. Codex wrote this as the first of three slices in docs/tasks/4.3a.md and stopped during the second at the 400-line limit (rule 3). This check-in holds only 4.2's files; the reviewer split them out and made no other changes.

Size: 62 non-spec lines.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX Leaf check-in: d219ac776f user: x86-1-glint tags: slice/4.3a

Claim: docs/tasks/4.3a.md hands out the rest of Phase 4 on aarch64 as three check-ins. The test guest gets an HVC call stub. Glint enters it at EL1 with eret under stage 2 over 3.5's guest space, and takes exits through its EL2 vectors. HVC calls go through the shared dispatcher. It also has Vcpu put SVM and EL2 behind one interface, since 4.3b, landing first, had bound Vcpu to Svm::State and serve tests SVM exit codes. The demo is Phase 4's on aarch64.

Passage: docs/WORKFLOW.md, Handing out a slice, step 1.

Demonstration: Vcpu's SVM ties were read in boot/vcpu.cr (Svm::State field, exit codes 0x7b and 0x400 in serve). EC values are in QEMU 11.1.2 target/arm/syndrome.h.

Size: one new task.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: e84b91daae user: x86-1-glint tags: trunk