Claim: README.md now opens with the text worked out by the maintainer and The One Place: what Glint is for, what it's made of (BQ2 defined where it first appears), how it's shaped, how it's built, a six-milestone success checklist, and the four virtues. The old opening and its Status section (Phase 1 and Track T done, Phase 2 next) are gone. Building, Layout, Working on Glint and Licence follow unchanged. Milestones 1-5 are marked not yet. Milestone 6 is marked done, with links to the x86_64 and aarch64 builds on x86-1.

Passage: The One Place's request (glint 5e43b80618, text in 0f2fb5db9d), from the maintainer's console thread (ocx-console f561f86cc3, d714496afc, 874aec9e34, 09cd94458a).

Demonstration: for milestone 6, command -v finds no python3, python, flex, bison, kconfig-conf, mconf, meson or ninja on x86-1, nor inside BQ2's seed. Glint's x86_64 build (3cefc212aa) and its aarch64 build inside the seed (940e9790c7) both ran there. The text above the checklist is used as given.

Size: the first 47 lines replaced by 118.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 1a2a966b51 user: x86-1-glint tags: trunk

Claim: Vcpu no longer names AMD's SVM. It reports a neutral ExitKind (call, halt, I/O, memory fault, shutdown, invalid state, other), which serve, GuestCalls and PortIO switch on. Its backend is chosen at compile time: Svm::State on x86_64, now holding all SVM exit decoding and the guest register array, and on aarch64 a stub El2::State whose creation fails with a status. Behaviour is unchanged. x86_64 boots are the same, and aarch64 still refuses hypervisor mode, now saying 'Mode: native (hypervisor requested; no aarch64 run loop yet)'. Part (ii) adds the EL2 run loop behind this interface.

Passage: slice 4.3b: 'Putting SVM behind the same interface as 4.3a, so nothing above the run loop knows which CPU it is on, is Loose Coupling.'

Demonstration: outside BQ2's seed, the vcpu, port I/O and EL2-stub specs and the x86_64 phase 4, fault and UART boots give 19 examples, 0 failures, 3 pending (aarch64). Codex reports the lazy-memory boot passing too. Inside the seed, the aarch64 boots give 15 examples, 0 failures, 1 pending (part ii), and the image check passes. The reviewer rebuilt BOOTAA64.EFI in the seed and booted --mode hypervisor with breakpoint: it prints the refusal reason, then 'Trap: breakpoint at ...' and 'breakpoint: resumed'. Codex wrote it from docs/tasks/4.3a-split.md part (i); the reviewer made no changes.

Size: +195/-97 non-spec lines, most of it moved; largest changed function Vcpu.boot, 1,288 bytes; BOOTX64.EFI 213,504 bytes, BOOTAA64.EFI 197,632 bytes.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX Leaf check-in: 9ff99a49fe user: x86-1-glint tags: slice/4.3a-i

Claim: docs/tasks/4.3a-split.md divides 4.3a after the first run stopped at 432 non-spec lines. (i) separates Vcpu from SVM so both machines share one interface, with no behaviour change. (ii) adds the EL2 backend, aarch64 hypervisor mode and 4.4's aarch64 half. It records the first run's finding: writing SP_EL0 with msr from ordinary code is UNDEFINED while Glint runs on SP_EL0, and that caused the attempt's panic.

Passage: docs/WORKFLOW.md, rule 3 (stop past ~400 lines and split).

Demonstration: the attempt's report and boot log (ESR 0x2000000 at the msr SP_EL0) are kept in the session scratchpad for part (ii). 4.2's aarch64 half is merged at 5649e3b699.

Size: one new task.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01TUH8KMXZyLk8eDgCjvQ9hX check-in: 653dca15b6 user: x86-1-glint tags: trunk